1. Field of the Invention
The present invention relates to interconnect structures for high-speed microprocessors, application specific integrated circuits (ASICs) and other high-speed integrated circuits (ICs). The present invention provides low dielectric constant, i.e., low-k, interconnect structures having enhanced circuit speed, structure stability during thermal cycling, precise values of conductor resistance, reduced fabrication cost, and improved ease of processing due to chemical-mechanical polishing (CMP) compatibility. Moreover, the inventive structures have a lower effective dielectric constant and improved control over metal line resistance as compared to conventional structures of the prior art.
2. Background of the Invention
Many ultra-low-k (on the order of about 3.5 or less) plus Cu interconnect structures of the dual damascene-type are known; See, for example, R. D. Goldblatt, et al., xe2x80x9cA High Performance 0.13 xcexcm Copper BEOL Technology with Low-K Dielectricxe2x80x9d, Proceedings of the International Interconnect Technology Conference, IEEE Electron Devices Society, Jun. 5-7, 2000, pgs 261-263. Such prior art interconnect structures include inorganic as well as organic dielectric materials as the interlevel or intralevel dielectric. It is widely accepted that dual-damascene structures are lower cost than single damascene or subtractive metal structures.
Typically, there are four essential problems associated with prior art dual damascene interconnect structures which include the following:
(i) Poor control over Cu line thickness (i.e., trench depth) and resistivity.
(ii) High coefficient of thermal expansion (CTE) of low-k dielectrics, which may eventually lead to failure during thermal cycling.
(iii) The inability of the ultra-low-k dielectrics to survive chemical-mechanical polishing (CMP).
(iv) Increased cost to fabricate the structures.
During fabrication of prior art interconnect structures, the depth of the trenches that become the metal line conductors (after metal fill and CMP) is often poorly controlled, and the trench bottom has a rough surface. This effect is exacerbated when performing reactive-ion etching (RIE) on porous dielectrics. A timed reactive-ion etching (RIE) process is typically used to etch the trenches, with time controlling the trench depth. Variations in the etch rate with feature size (trench width) from day to day, and across the wafer, lead to large variations in the trench depth which, in turn, leads to large variations in the metal conductor resistance. Roughness at the trench bottom leads to higher capacitance, leaky electron current between metal lines, crosstalk, noise, power dissipation and ultimately, to poorer device performance and poorer reliability.
Common solutions to the aforementioned problems add extra processing steps, including deposition of a discrete etch stop layer in a separate plasma-enhanced chemical vapor deposition (PECVD) tool, thus raising the cost of fabricating the desired low-k plus Cu interconnect structure.
Additionally, low-k dielectrics plus Cu interconnect structures of the dual damascene-type fail during thermal cycling tests due to a high-CTE of the dielectric surrounding the vias. Moreover, commonly used porous low-k dielectrics do not survive CMP. Instead, prior art porous low-k dielectrics tend to be delaminated and removed during the CMP process. Furthermore, prior art etch stop layers are made from vacuum-based PECVD deposition tools that are costly to purchase and maintain.
In view of the above problems in the prior art, there is a continued need for providing new and improved low-k dielectric interconnect structures of the dual damascene-type that overcome the drawbacks mentioned above.
One object of the present invention is to provide a low-k dielectric plus metal conductor interconnect structure of the dual damascene-type in which precise and uniform control over metal conductor resistance is obtained without thickness variation of the conductors.
Another object of the present invention is to provide a robust low-k dielectric plus metal conductor interconnect structure that is stable during thermal cycling due to a low-CTE of the dielectric surrounding the vias.
A further object of the present invention is to provide an interconnect structure that is easy to process because the structure survives CMP without delamination or other failures.
A yet further object of the present invention is to provide a low-k dielectric plus metal conductor interconnect structure which includes no additional processing steps thereby not significantly increasing the production cost of the structure.
An even further object of the present invention is to provide a low-k dielectric plus metal conductor interconnect structure which comprises a multilayer of spun-on dielectrics.
An additional object of the present invention is to provide a low-k dielectric plus metal conductor interconnect structure in which the process used in forming the same avoids the use of costly vacuum based deposition tools.
These and other objects and advantages are achieved in the present invention by providing a metal wiring plus low-k dielectric interconnect structure of the dual damascene-type wherein the conductive metal lines and vias are built into a hybrid low-k dielectric structure which includes two spun-on dielectrics that have different atomic compositions and at least one of the two spun-on dielectrics is porous. The two spun-on dielectrics used in forming the inventive hybrid low-k dielectric structure each have a dielectric constant of about 2.6 or less, preferably each dielectric of the hybrid structure has a k of from about 1.2 to about 2.2. By utilizing the inventive hybrid low-k dielectric structure excellent control over metal line resistance (trench depth) is obtained, without added cost. This is achieved without the use of a buried etch stop layer, which if present, would be formed between the two spun-on dielectrics.
In accordance with the present invention, the spun-on dielectrics of the hybrid low-k dielectric structure have distinctly different atomic compositions enabling control over the conductor resistance using the bottom spun-on dielectric (i.e., via dielectric) as an inherent etch stop layer for the upper spun-on dielectric (i.e., line dielectric).
In one aspect of the present invention, an interconnect structure is provided which comprises:
a substrate having a patterned hybrid low-k dielectric formed on a surface thereof, said patterned hybrid low-k dielectric having an effective dielectric constant of about 2.6 or less and comprising a bottom spun-on dielectric and a top spun-on dielectric, wherein said bottom and top spun-on dielectrics have different atomic compositions and at least one of said spun-on dielectrics is porous;
a polish stop layer formed on said patterned hybrid low-k dielectric; and
metal conductor regions formed within said patterned hybrid low-k dielectric.
Another aspect of the present invention relates to a hybrid low-k dielectric which can be used in fabricating interconnect structures of the dual damascene-type. Specifically, the inventive hybrid dielectric comprises a bottom spun-on dielectric and a top spun-on dielectric, wherein said bottom and top spun-on dielectrics have dielectric constants of about 2.6 or less, different atomic compositions and at least one of said dielectrics is porous.
A further aspect of the present invention relates to a method of forming the aforementioned interconnect structure. Specifically, the method of the present invention comprises the steps of:
(a) forming a hybrid low-k dielectric on a surface of a substrate, said hybrid low-k dielectric having an effective dielectric constant of about 2.6 or less and comprising a bottom spun-on dielectric and a top spun-on dielectric, wherein said bottom and top spun-on dielectrics have different atomic compositions and at least one of said spun-on dielectrics is porous;
(b) forming a hard mask on said hybrid low-k dielectric, said hard mask including at least a polish stop layer;
(c) forming an opening in said hard mask so as to expose a portion of said hybrid low-k dielectric;
(d) forming a trench in said exposed portion of said hybrid low-k dielectric using said hard mask as an etch mask;
(e) filling said trench with at least a conductive metal; and
(f) planarizing said conductive metal stopping on said polish stop layer.